Intel-Arm Collaboration Is Under Way


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Intel Foundry Services and Arm agreed last month to optimize Arm’s IP for Intel’s upcoming 18A process technology (1.8 nm). The collaboration will focus on mobile designs and will undertake design technology co-optimization (DTCO) and system technology co-optimization (STCO), which means that Arm’s IP will be optimized both for Intel’s forthcoming production node and for the company’s advanced packaging technologies.

Intel Foundry Services and Arm will jointly fine-tune Arm’s IP using the DTCO methodology for Intel’s 18A manufacturing process to optimize performance, power and costs of upcoming designs. One of the key fruits of this collaboration will be development of “an Arm-based mobile SoC and silicon technology demonstration and reference platform for chip designs,” which is a rather broad definition of the work.

Meanwhile, Intel and Arm confirm that the work has commenced.

“The work will validate the performance, power and area utilization of Arm SoC designs on the Intel 18A process,” a spokesperson for Intel told EE Times.

“We are building custom IP to ensure optimal power, performance and area for Arm-based SoC design,” a spokesperson for Arm explained to EE Times. “With this announcement, we enable one more option to our licensees to choose from when they target advanced nodes for Arm-based SoC design.”

Hierarchies in system technology co-optimization.
Hierarchies in system technology co-optimization. The differences between device optimization, DTCO, 3DIC and STCO are illustrated. (Source: Intel)

In search of new customers

While initially the “multigeneration” collaboration will focus on mobile SoC projects and appropriate Arm IP (e.g., Cortex-A CPU IP, Mali GPU IP, etc.), the two companies said that the scope of the collaboration may be expanded to automotive, aerospace, data center (e.g., Neoverse), IoT and government applications. While “government applications” is a rather ambiguous term, keep in mind that Intel’s 18A has already been selected by the U.S. Department of Defense, so perhaps it will be a little easier for Arm licensees to address the needs of the U.S. Army with optimized Arm IP.

Meanwhile, it is hard to overestimate the general importance of the Intel Foundry-Arm announcement, as it ensures that IFS will be able to produce SoCs based on optimized Arm IP, just like its rivals from TSMC and Samsung Foundry.

On the other hand, Arm needs to ensure that its cores can be made by as many chip producers as possible on as many fabrication technologies as possible.

“Arm needs to make sure its cores are validated on as many process nodes as possible, but for Intel, it gives them a selling point for lots of Arm ecosystem players, which has done very well for TSMC,” said Ian Cutress, principal analyst at More Than Moore. “Intel is looking to grow customers by orders of magnitude, whereas for Arm, this is ‘another step.’”

“IFS wants to have as much IP as possible to enable customers to build products,” said David Kanter, president of Real World Tech and inference and power co-chair at MLPerf. “The more IP that is available on IFS, the lower the friction for a customer.”

“This helps align Intel’s foundries with the needs of the industry, which is a focus on performance efficiency,” said Jim McGregor, principal analyst at Tirias Research. “It also makes the foundry market more competitive by offering another leading-edge foundry.”

The scope of the collaboration is currently limited to mobile SoCs, which may be somewhat surprising given Intel’s focus on data center hardware in recent years and its experience with large chips in general, but it makes a lot of sense both for Arm and Intel Foundry, as smartphone SoCs are among the largest revenue sources for Arm and represent a good opportunity for Intel Foundry.

“Right now, with Softbank and IPO, Arm is limiting the projects it is doing, so it is picking and choosing the highest-benefit opportunities,” Cutress said. “Mobile SoCs is a good target because IFS only really has high-performance nodes to offer, and die sizes are small [~100–150 mm2], which are better for yield ramp compared with large, 700-mm2 data center silicon. Automotive does not always need leading edge, so mobile SoCs are good. If we look at TSMC, 34% of its revenue is smartphones and 44% is HPC [mobile and performance], so IFS/Arm going after mobile IP validation makes sense.”

Not only mobile

Intel itself considers its 18A process as the node that will have an indisputable lead when it comes to performance, power and transistor density. The company originally planned that its 18A manufacturing technology would be the first to use ASML’s High-NA Twinscan EXE EUV scanners, with a 0.55 numerical aperture sometime in 2025, but eventually, the company disclosed that it could use existing 0.33-NA EUV tools with double patterning instead of next-generation machines in the second half of 2024. Meanwhile, to reduce EUV double patterning and optimize 20A and 18A costs, the company will adopt Applied Materials’ Centura Sculpta pattern-shaping tool.

If Intel manages to provide the highest performance efficiency and transistor density with its 18A manufacturing process and offer it at good financial terms, fabless chip designers will be inclined to use it. Furthermore, with optimized standard Arm IP, the process technology promises to be even more attractive for SoC developers.

“The goal of supporting Arm cores is that they are used across a wide range of products and are a ‘standard building block’ for many SoCs,” Kanter noted.

While the announcement itself is very general, the collaboration promises to provide a lot of possibilities for Arm’s licensees, including Qualcomm, which has already announced plans to use Intel’s 18A fabrication process but never disclosed for what kinds of products. MediaTek is another major mobile SoC developer signed up to use IFS’s capacity, but it has yet to show interest toward Intel’s 1.8-nm–class production node. There could be other less obvious beneficiaries from the IFS-Arm announcement, analysts said.

“Qualcomm has expressed interest, but until a company starts handing over money and investing design teams, I am skeptical,” Cutress said. “MediaTek has expressed interest, but not so much on mobile SoCs so far. That leaves few other major players—Apple [not until Intel has leadership], Samsung [would be weird but not impossible] and Unisoc [might be a way around the issues they are having with the U.S. government].”

Qualcomm already uses customized high-performance Arm cores in its Snapdragon SoCs, and in the coming years, the company plans to adopt highly custom Nuvia-developed Arm microarchitecture across a range of products. Therefore, it is less likely to be interested in implementation of standard high-performance Arm Cortex cores, but it can still take advantage of Arm technology optimized for Intel’s 18A.

“Even in the case of Qualcomm, many mobile SoCs use smaller cores either as user-visible processors [e.g., the ‘little’ core] or as a service processor,” Real World Tech’s Kanter said. “In the mobile world, MediaTek tends to use standard Arm cores throughout their product line.”

“Qualcomm is the obvious [beneficiary] that comes to mind, but Apple could benefit from it,” Tirias Research’s McGregor said. “MediaTek, which has a modem partnership with Intel, could benefit from it. Google could benefit from it. Other handset OEMs considering making their own chips could also benefit from it.”

In fact, there are a lot of non-mobile applications—aimed at anything from automotive to data centers—that can benefit from standard Arm cores optimized for Intel’s 18A node, analysts from More Than Moore and Real World Tech said.

“There is also a lot of ‘mobile SoC-like’ ASICs out there that you might not think of: IPMI silicon, ACAPs Xilinx/hardened FPGAs, controllers, etc.,” Cutress said. “Requirements on [automotive infotainment] silicon are not as strict.”

“Arm IP is potentially useful in automotive infotainment,” Kanter said. “Just look at GM’s adoption of Android. Android runs best on Arm.”

“The mobile segment is just the tip of the iceberg,” McGregor said. “The CE and embedded markets account for even more Arm components.”

In fact, Intel Foundry and Arm collaboration could quickly extend to more demanding data center applications, he said.

“They can extend it very quickly,” McGregor added. “You have to remember that Intel is and has been an Arm licensee for many, many years. Intel is familiar with the architecture. The only limitation is demand. If the opportunity arises, I am sure we will see these products running at Intel even though they will compete with other Intel products.”

DTCO meets GAA transistors and backside power delivery

When it comes to foundries, DTCO methodologies have been around for some time, so IFS is certainly not the first here. Actually, most of Intel’s own CPU cores are architected for particular production nodes, representing a good example of DTCO advantages when it comes to frequencies and power, albeit at an IDM, so Intel is certainly not new to this methodology as well.

Intel’s 18A fabrication process will be the company’s second node (after 20A) to adopt gate-all-around (GAA) transistors that the company calls RibbonFET and backside power delivery network (PDN), branded as PowerVia. Intel’s 20A and 18A are two fabrication technologies that are developed both for Intel itself and for IFS customers. Furthermore, both provide an abundance of options for DTCO.

Intel’s RibbonFET GAA transistor architecture stacks four nanoribbons to achieve the same drive current as multiple fins, but in a small footprint.
Intel’s RibbonFET GAA transistor architecture stacks four nanoribbons to achieve the same drive current as multiple fins, but in a small footprint. (Source: Intel)

GAAFETs offer several key advantages compared with planar transistors and FinFETs, such as significantly minimized leakage current, as the gates now surround all four sides of the channel.

Also, in GAA transistors, it is possible to alter the nanosheets’ width for a specific production process or even within a particular chip design, enabling the fine-tuning of performance (with increased width), energy consumption (with reduced width) and die area.

For mobile SoC designs, GAA transistor’s reduced leakage current is an indisputable benefit. Tailoring transistor architecture for mobile designs further could enable additional benefits when it comes to power and performance. Meanwhile, adjusting standard cells, developing mobile-specific libraries and implementing Arm IP on Intel’s 18A should enable further performance, power, area and cost optimizations on the transistor level. Unfortunately, Intel Foundry and Arm have not confirmed any specifics related to transistor design optimization.

Feeding transistors has been a challenge on thinner nodes for a while due to increasing contact resistance and IR drop, resulting in lost energy, lower performance and high temperatures. Backside PDN (dubbed PowerVia by Intel) moves power wires away from data I/O wires, simplifying connectivity and enabling a more sophisticated PDN.

“In general, by eliminating the need for power routing on the front side of the wafer, more resources become available to optimize signal routing and reduce delay,” the Intel spokesperson said. “This enables us to optimize for performance, power or area depending on the product needs.”

Intel’s backside PDN, PowerVia, that separates power and signal lines and shrinks the standard cell size.
Intel’s backside PDN, PowerVia, that separates power and signal lines and shrinks the standard cell size. Power wires are placed beneath the transistor layer, on the backside of the wafer. (Source: Intel)

Power delivery tends to differ from chip design to chip design.

For example, CPUs for client and data center processors are customized to meet different performance requirements, and therefore, they need different PDNs. Server processors are capable of handling heavy workloads steadily and can briefly enhance their clocks when demand peaks.

On the other hand, client CPUs are optimized for burst behavior in general, as they usually remain inactive or work under low loads—but when a resource-intensive workload is launched, these processors need to quickly (within microseconds) boost their performance from idle to maximum speed, sometimes even surpassing it, to ensure smooth user experience. Smartphone SoCs are designed to respond to demands even quicker, and they need their own PDN design.

Optimizing the PowerVia PDN for Arm IP aimed at smartphone SoCs could bring numerous advantages in terms of performance and power consumption when compared with Intel’s vanilla PowerVia PDN that is likely designed to serve a wide range of applications. Again, formally, Intel Foundry and Arm did not confirm plans to tailor RibbonFETs and PowerVia for standard mobile Arm IP as parts of the ongoing collaborative work.

“I would expect Intel’s GAA to be higher-performance than other foundry options—in part because of the adoption of PowerVia [and also differences in transistor implementation],” Kanter explained. “So that would potentially translate into better frequency or lower power at similar frequencies. Intel’s PowerVia is part of 20A and 18A, so I would expect the optimization of Arm IP for Intel’s process would include PowerVia as well. PowerVia generally seems likely to provide a small performance benefit through better power delivery [say, 3% to 7%] and a nice area reduction [15% to 20%], based on an analysis I have seen.”

Cutress chimed in: “While the collaboration between Intel Foundry and Arm will bring a number of benefits to customers planning to implement Arm’s mobile IP, IFS is willing to work closely with every big-enough customer to improve PPA.

“Nothing specific in Arm means Intel’s GAA would get a benefit; the transistor and the architecture are independent,” he added. “I think IFS will do what it can to give its primary customers additional benefits, especially if it is a big player [Apple, Qualcomm], regardless of the chip or the architecture.”

McGregor said he does not see any specific benefit to Arm over other architectures: “The advancements in semiconductor/transistor design will be a benefit to the entire industry.”

An example of multi-tile client system-in-package.
An example of multi-tile client system-in-package (Source: Intel)

Another detail that Intel Foundry and Arm mentioned in prepared remarks was intention to optimize the target platforms “from applications and software through package and silicon,” essentially implying STCO. While Intel admits that both EMIB (2.5D) and Foveros (3D) packaging technologies are in the cards, the company is not ready to share any additional details.

“The collaboration would take both 2.5D and 3D packaging technologies into consideration,” Intel said.

Bringing disaggregated designs to the mobile world, which has been focused on highly integrated SoCs for a while, will mark a milestone for the industry. Though it remains to be seen what exactly Intel and Arm plan to do here, as the framework of the announcement is currently limited to Intel’s 18A production node, whereas a disaggregated design implies usage of several nodes to optimize costs. Furthermore, the costs of advanced packaging are very high now, analysts note.

Qualcomm presented on the topic of chiplet strategies and packaging at IEEE conferences in the past two years, Cutress said, adding, “It will happen, if not in smartphones, then laptops, where there is z-height available. The main point of contention is cost—chiplet packaging is still very expensive.”

Kanter said advanced packaging in mobile will depend on cost: “Right now, most advanced packaging techniques are relatively expensive to implement. Look at the cost delta for 3D stacking. Once the benefits become greater or we can reduce cost through more mature flows, that could enable more advanced mobile packaging.”

McGregor said disaggregated mobile SoC designs are not in the near future: “You have to remember that there are size, power, size and cost constraints for mobile. Thus, there are still advantages to having a single die. At least not until the [advanced packaging] cost comes down or the economics of having multiple dies change.”

In fact, Arm also says that while disaggregation of mobile SoCs is possible, it must be evaluated very carefully.“There are many factors in play,” the Arm spokesperson said. “The cost structure in mobile needs to be evaluated, and importantly, RTL needs to be optimized to ensure the disaggregation and package technology can be taken advantage of.”

But STCO will likely not be limited to packaging only and will involve everything from thermal management to production flows, Kanter said.

“I think STCO encompasses more than just packaging,” he said. “Part of it is integrating thermal management, power delivery and packaging into the overall manufacturing flows.”

System technology co-optimization of a computing system.
System technology co-optimization of a computing system (Source: Intel)

Broad geography

One of the advantages that Intel expects IFS to have over competitors is that it is going to have 18A-capable production capacity both in the U.S. and Europe, which will enable IFS’s customers to diversify their supply chains.

An Intel fab in Oregon.
An Intel fab in Oregon (Source: Intel)

Because the current collaboration is limited to Arm’s mobile IP, whereas leading mobile SoC developers are located in the U.S. (Apple, Qualcomm), Taiwan (MediaTek) and China (Unisoc), it remains to be seen whether it is important for them to produce their SoCs in the U.S. or Europe, keeping in mind that actual devices will still be assembled in China, India or southeast Asian countries.

Yet, given the current geopolitical tensions, a diversified supply chain may be an advantage, per se, so making leading-edge chips on 18A node both in the U.S. and Europe (eventually) is an indisputable trump card that Intel Foundry will have, Kanter and McGregor said.

“Ability to produce both in the U.S. and Europe is an advantage, especially for military/government applications,” McGregor said.

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