Intel’s embedded multi-die interconnect bridge (EMIB) technology—aiming to address the growing complexity in heterogeneously integrated multi-chip and multi-chip (let) architectures—made waves at this year’s Design Automation Conference (DAC) in San Francisco, California. It delivers advanced integrated IC packaging solutions that encompass planning, prototyping, and signoff across a broad range of integration technologies such as 2.5D and 3D IC.
At DAC, Intel exhibited tie-ups with key EDA and IP partners to ensure that their heterogenous design tools, flows and methodologies, and reusable IP blocks are fully enabled and qualified to support EMIB assembly technology.
Figure 1 A silicon bridge is embedded inside a package to connect multiple dies. Source: Intel
At the heart of these initiatives was Intel Foundry’s Package Assembly Design Kit (PADK), which enables engineers to create EMIB-based package designs. Intel’s PADK—comprising a design guide, rules, and stack-up that enable chip designers to complete and verify an EMIB design efficiently—aims to address chip design complexity and facilitate EDA tool enablement.
PADK enables reference flows that support tools from all major EDA vendors to facilitate a PADK-driven assembly verification. Below is a sneak peek at Intel’s Foundry’s recent collaborations with major EDA vendors for EMIB enablement.
Collaboration with EDA trio
Simens EDA
At DAC 2024, Siemens EDA announced tool certifications for EMIB enablement for designing highly complex ICs and advanced packaging. The certifications include Solido SPICE—part of the Solido Simulation Suite software—for the foundry’s Intel 16 and Intel 18A process nodes.
Earlier, in February 2024, Siemens EDA announced the availability of the EMIB reference flow to allow design engineers carry out early package assembly prototyping, hierarchical device floorplanning, co-design optimization, and verification of the complete detailed implementation. The reference flow, built around Intel Foundry’s PADK, enables engineers to tackle the full range of critical tasks needed for a successful design and tape-out.
Figure 2 The EMIB reference flow enables design engineers to create high-density interconnect for heterogeneous chips. Source: Siemens EDA
Synopsys
Synopsys also exhibited a multi-die reference flow for Intel Foundry on the DAC 2024 floor. Powered by Synopsys.ai EDA suite, it aims to provide designers with a comprehensive and scalable solution for fast heterogeneous integration using EMIB assembly technology.
The reference flow, enabled by Synopsys 3DIC Compiler, provides a unified co-design and analysis solution to accelerate the development of multi-die designs at all stages from silicon to systems. Moreover, Synopsys 3DSO.ai, which is natively integrated with Synopsys 3DIC Compiler, enables optimization for signal, power, and thermal integrity.
Ansys, a supplier of electrothermal tools currently in the process of being acquired by Synopsys, is also providing multi-physics signoff solutions for Intel’s 2.5D chip assembly technology, which uses EMIB technology to connect the die flexibly and without the need for through-silicon vias (TSVs). Its RedHawk-SC Electrothermal EDA platform enables multi-physics analysis of 2.5D and 3D ICs with multiple dies.
Cadence Design Systems
Cadence, another member of EDA trio, has also joined hands with Intel Foundry to certify an integrated advanced packaging flow utilizing EMIB technology to address the growing complexity in heterogeneously integrated multi-chip(let) architectures. This EMIB flow enables design teams to seamlessly transition from early-stage system-level planning, optimization and analysis to DRC-aware implementation, and physical signoff without converting data between different formats.
EDA tool enablement
Intel, which has led the packaging technology development curve for a couple of decades, has now launched two advanced packaging technologies to scale silicon area by connecting multiple dies in a single package. While EMIB connects multiple chips side by side in a package, chips are stacked on top of one another in a 3D fashion in Foveros.
Rahul Goyal, VP and GM for product and design ecosystem enablement at Intel, says EMIB technology embodies a differentiated approach to multi-die assembly compared to traditional stacking techniques. Intel has already implemented EMIB technology in its own chips, including GPU Max Series (code-named Ponte Vecchio), 4th Gen Intel Xeon and Xeon 6 processors, and Intel Stratix 10 FPGAs.
Figure 3 Intel Foundry developed EMIB to connect multiple dies in a single package. Source: Intel
However, EMIB, like other advanced packaging technologies, presents new challenges related to the design and packaging complexities of multi-die architectures. So, incorporating a variety of EDA tools into Intel’s PADK is a good start. It will help chip designers implement and verify EMIB designs effectively and efficiently.
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