PCIe 5.0 Retimer Supports CXL 2.0, Extends Links

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Kandou recently introduced the Regli KB9003, one of the world’s first PCIe 5.0 retimers that also supports the CXL 2.0 protocol, which promises to become a must-have feature for next-generation data center applications that use accelerators (such as compute GPUs or FPGAs), memory-expansion boards or persistent memory. Samples of the chip are set to be available in Q3, and the company hopes to initiate mass production of its Regli KB9003 early next year.

Kandou’s Regli KB9003 is a versatile bidirectional, 16-lane PCIe 5.0 retimer that is aware of the CXL 2.0 protocol and supports data-transfer rates of up to 32 GT/s. The device is designed to extend the PCIe trace length between the root complex and its endpoints, ensuring the preservation of signal integrity along the way, which is accomplished by dynamically offsetting channel losses up to 36 dB (across power and voltage variations) using Kandou’s Autonomous Receiver Equalization (ARxE) technology.

The Kandou Regli KB9003 PCIe 5.0 retimer.
The Kandou Regli KB9003 PCIe 5.0 retimer (Source: Kandou)

One of the main features of the Regli KB9003 is its support of CXL 2.0 retiming mode for CXL.io, CXL.cache for cache coherency and CXL.memory for memory coherency protocols that are used for I/O, accelerators, memory-enhancing devices and persistent memory. The chip provides a common clock mode via an elastic buffer and a separate reference clock with independent spread (SRIS) mode, which supports diverse packet-size configurations. The retimer also features a drift buffer mode designed to achieve ultra-low–latency targets, which are crucial for CXL. Like any retimer, it adds latency itself, but Kandou says it is less than 20 ns. Additional features include various control interfaces, multiple clock modes, secure boot and on-board diagnostics.

Block diagram of the Regli KB9003 PCIe 5.0 retimer.
Block diagram of the Regli KB9003 PCIe 5.0 retimer (Source: Kandou)

Kandou does not disclose which process technology it uses to make its Regli KB9003 but says it consumes a rather sizeable 14.4 W. It is noteworthy that the company plans to offer the chip in different packages to meet the requirements of various applications.

Retimers’ importance growing

PCIe has become a ubiquitous interface for client and server PCs due to its consistent evolution and regular performance improvements. But increasing data-transfer rates to 32 GT/s over copper interconnects brings a number of challenges when it comes to routing, signal loss, noise, impendence and EMI shielding. Routing PCIe 5.0 interconnections is complicated in client PCs. But for server or automotive applications, it gets significantly harder.

The difference between a retimer and a redriver.
The difference between a retimer and a redriver (Source: Kandou)

To enable long PCIe 5.0 interconnects in servers, one has to use PCIe 5.0 retimers, tiny mixed-signal analog/digital devices that can fully restore data, isolate the integrated clock and transmit a renewed version of the data using a clear and uncluttered clock signal. By contrast, redrivers equalize and re-amplify signals that have degraded over long transmission distances, but the way they work, they also amplify noises. Modern systems for artificial-intelligence and high-performance computing (HPC) applications can use as many as 20 PCIe 5.0 retimers, according to Kandou.

“On the AI systems, it is difficult to say definitively [how many retimers per system are used], as there are a few architectures, but the high-end we have seen is 20 in a platform,” said Subhash Roy, VP of product management at Kandou. “I am being vague due to each vendor having different architectural splits, CPU board versus riser card versus AI board due to power/size.”

Kandou’s Subhash Roy.
Kandou’s Subhash Roy (Source: Kandou)

One of the main challenges solved by retimers is enabling longer connections within the system (or even outside of it) by offsetting channel losses. When it comes to PCIe 5.0, the length of traces gets significantly shorter when compared with previous versions of the specification. While there are many variables here, the Regli KB9003 can extend trace length all the way to 11 inches (279 mm).

“For PCIe links, the loss budget covers the root complex package, vias on the system board, trace length and connectors,” Roy said. “The trace length varies based on the choice of materials from low-loss to ultra-low–loss and environmental conditions, such as temperature and humidity. Regli can extend the trace length reach by 5 to 11 inches, depending on these design requirements.”

The importance of retimers is hard to overestimate for high-performance machines for AI and HPC applications running multiple GPUs, such as Nvidia’s DGX H100. Meanwhile, the importance of the Regli KB9003 will only grow, as the adoption of CXL 2.0 will expand in the coming years.

“With the explosion of data required to fuel cutting-edge workloads like AI and HPC, the need for advanced I/O technologies like PCIe 5.0 and CXL 2.0 on Intel’s Xeon platforms has never been greater,” said Jim Pappas, director of technology initiatives at Intel. “As Intel continues to increase compute performance across its product roadmap, it’s great to see retimer products for these important industry standards innovating in parallel.”

A riser card with Kandou’s Regli KB9003.
A riser card with Kandou’s Regli KB9003 (Source: Kandou)

Kandou’s Regli KB9003 retimers are set to sample already this quarter and then ship in commercial quantities starting in early 2024. Keeping in mind that we are dealing with data-center–grade solutions, it will take some time for hyperscalers as well as makers of servers to validate these retimers, and then they are going to start using them, perhaps around the time when CXL 2.0-supporting accelerators and memory-expansion solutions will become more widespread.

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